By Dimitris Gizopoulos
This is a brand new kind of edited quantity within the Frontiers in digital trying out ebook sequence dedicated to contemporary advances in digital circuits checking out. The booklet is a accomplished elaboration on vital subject matters which trap significant learn and improvement efforts this present day. "Hot" themes of present curiosity to check know-how neighborhood were chosen, and the authors are key individuals within the corresponding topics.
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Extra resources for Advances in Electronic Testing: Challenges and Methodologies (Frontiers in Electronic Testing)
Copper has only a single via/wire interface, since both vias and wires are deposited together. The absence of the metal etch and the reduced number of interfaces can result in a lower defect level for copper metalization than aluminum. However, there are some specific new defect mechanisms associated with copper. These were particularly troublesome in the early days of copper processing, but are now at more acceptable levels. 3 The term “damascene” comes from metal inlaid with gold or silver, an intricate craft associated with the city of Damascus.
If path slack is low enough that values are latched before switching is complete, Byzantine behavior can result, as shown in Figure 1-17. In theory, increasing clock speed could eliminate this problem, by latching data at the “latch 0” point rather than the “latch 1” point, but in practice running such tests is difficult. As a result, diagnosis of short-induced delay faults should consider Byzantine behavior a strong possibility. Also, as was seen with the copper voids, resistance is not a fixed property for defects.
Logical behavior—Each fault is confined to a single location in the circuit and its effect is readily modeled as a boolean equation. As a result equivalence relationships can be developed: A stuck-at 0 fault on the output of an AND gate is equivalent to a stuck-at 0 fault on any of its inputs. Tractability—The number of faults is directly proportional to the size of the circuit, so very large circuits can be analyzed. Stuck-at fault based test generation and simulation can be applied to designs containing millions of logic gates in a single pass.