Download Analog Circuit Design Techniques at 0.5V (Analog Circuits by Shouri Chatterjee, K.P. Pun, Nebojša Stanic, Yannis PDF

By Shouri Chatterjee, K.P. Pun, Nebojša Stanic, Yannis Tsividis, Peter Kinget

This publication tackles demanding situations for the layout of analog built-in circuits that function from ultra-low strength provide voltages (down to 0.5V). insurance demonstrates the sign processing circuit and circuit biasing techniques throughout the layout of operational transconductance amplifiers (OTAs). those amplifiers are then used to construct analog approach services together with non-stop time clear out and a pattern and carry amplifier.

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Extra info for Analog Circuit Design Techniques at 0.5V (Analog Circuits and Signal Processing)

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5V) M2A M6 M3A M3B IL R1A R1B Von M2B VL Vop M5A M5B Vip Vin M1A M4A M4B Vbn M1B VNR (b) Fig. 8: Circuit development of the gate-input OTA. (a) Basic configuration. (b) Schematic of one stage of the gate-input OTA. 5 V ) M2A M1A Vbn R1A M5A M4A M6 M7 R1B VL M5B M4B M3B VNR M2B Vin M1B - M9A RC M8A M10A CC CL V out M11A R2A M12A M13 M14 R2B VL M12B M10B RC M9B M8B CC Vout+ CL M11B Fig. 9: Two-stage, fully differential, gate-input OTA, with Miller compensation. 28 2 Fully Differential Operational Transconductance Amplifiers (OTAs) von + rds7 rds1 || rds2 || rds3 || rds4 R1 vc + rds1 || rds2 || rds3 || rds4 R1 vop + gm1vin gm1vip + vip + vip gm4vop gm4von - (gm2+gmb2)vc (gm3+gmb3)vff + vff - gm5vip (gm3+gmb3)vff gm5vin 1/(gm6+gmb6) Fig.

Simulations of the open-loop phase response, adjusted for board parasitic capacitances, are shown compared to measurements, in Fig. 20. Measurements of the gain and phase response of the body-input OTA, in closed loop, are shown in Fig. 21. The measured output noise in the closed loop is shown in Fig. 22. The initial slope is a result of 1/f noise, the peaking in the noise response close to the gain-bandwidth frequency is because of the low phase margin. Measured results, in all cases, match well with simulations.

A current source is designed using a single nMOS device. To increase the inversion level of this device, the bias voltage is applied both, through the gate and the body. A replica of this current source is used in the biasing circuit as shown in Fig. 13. A current is drawn by the device which creates a voltage drop across the resistors. 25 V. 15 V. This well defined IR voltage drop is ratio-ed and transferred to the level shifters in Fig. 9 through M7 , R1A , R2A and M14 , R2A , R2B . A compensating capacitor, CCL , is used to stabilize the feedback loop.

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