By Ivan S. Kourtev
History of the booklet The final 3 many years have witnessed an explosive improvement in built-in circuit fabrication applied sciences. The complexities of cur lease CMOS circuits are attaining past the a hundred nanometer function measurement and multi-hundred million transistors in step with built-in circuit. to totally take advantage of this technological power, circuit designers use refined Computer-Aided layout (CAD) instruments. whereas assisting the skills of innumerable microelectronics engineers, those CAD instruments became the permitting issue answerable for the profitable layout and implemen tation of hundreds of thousands of excessive functionality, huge scale built-in circuits. This learn monograph originated from a physique of doctoral disserta tion learn accomplished via the 1st writer on the college of Rochester from 1994 to 1999 whereas lower than the supervision of Prof. Eby G. Friedman. This examine specializes in matters within the layout of the clock distribution internet paintings in huge scale, excessive functionality electronic synchronous circuits and especially, on algorithms for non-zero clock skew scheduling. throughout the improvement of this learn, it has turn into transparent that incorporating timing matters into the winning built-in circuit layout technique is of primary value, really in that complicated theoretical de velopments during this quarter were gradual to arrive the designers' desktops.